Test Method for Internal Tristate Drivers
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
A test method is described which permits testing the high impedance state of chip-internal tristate drivers that are not accessible from the outside. The figure shows four tristate drivers TSD1 to TSD4, connected to associated receivers REC1 to REC4 through a bus, and the first test step. The bus is used as a dynamic storage element. The high impedance state of the tristate drivers is tested relative to the information stored on the bus. If the high impedance state has been reached, the stored information will be retained, whereas otherwise it will be altered. The receiving circuits are used to read information from the bus. Testing proceeds as follows: 1. - TSD1, TSD2, TSD3 are tested. - TSD1, TSD2, TSD3 are in the high impedance state, the data stored being "1". - TSD4 writes a "0" onto the bus.