Random-Access Memory Diagnostic
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
The present diagnostic will test a non-contiguous random-access memory (RAM) subsystem which provides functional verification of addressability, data bus lines and parity logic without the need for checking each non- contiguous segment separately. The present diagnostic can be used on both contiguous and non-contiguous RAM systems. The test sequence for the diagnostic of the present invention is as follows: 1. Test the RAM logic at the beginning of each RAM section to: a) verify that an even and odd parity word ('A55A' and 'A55B') can be written and read back on both even and odd boundaries, and b) verify that an even and odd parity byte ('5A' and '5B') can be written and read back on both even and odd boundaries. 2.