Memory Error Detection Using Error Correction Code Hardware
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08
A method of detecting uncorrectable (double-bit) errors in memory is described. The method provides a means of testing random-access memory (RAM) memory to determine if the memory has failed in such a way that uncorrectable errors will occur. So that the error detection runs quickly, this should be done without specifically testing all possible data patterns for each memory address. The hardware used to read memory contains automatic single error correcting code logic (ECC) which hides the exact failing bit. This logic cannot be disabled. However, if a multiple bit (uncorrectable) error occurs, the hardware will return the exact data as read from memory. It will also indicate if error correction is performed due to a single bit error, or if an uncorrectable error has occurred.