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Logic Partitioning in VLSI Chips to Improve Failure Analysis

IP.com Disclosure Number: IPCOM000059803D
Original Publication Date: 1986-Jan-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Floyd, R Torres, A [+details]

Abstract

A method is described to speed up the failure analysis of chip defects on very large-scale integrated (VLSI) chips by partitioning the logic. The time required to analyze defects on VLSI chips due to the increasing number of devices on a chip can be a problem. One of the physical design concepts that is being employed more and more to make this complexity more manageable is called a macro design concept. Logic is broken up into partitions, such as an ALU, ROS, or an Incrementer. As these macros become larger and larger, the ability to quickly find a defect decreases. In the new technique, all logic macro outputs that would not normally go to a latch when connected to another logic macro are forced to go to a latch. The L1 terminal of the latch would then feed all the places the macro signal was feeding.