100% Error Detection Scheme for Carry Save and Carry Look-Ahead Adders
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
This circuit allows 100% error detection of Carry Save and Carry Look- Ahead Adders with minimal additional circuitry. Selective duplicate circuits are utilized judiciously to enable all logic circuits involved to be checked 100%. The 100% error detection is achieved by generating parity S'p from the duplicated carries C1d-Cid from the first stage, the duplicated carries C'1d-C'i-1d from the second stage, and the parities of the three inputs to the adder, Xp, Yp, Zp, and comparing it with the parity of the output of the adder S'0-S'i . The duplicated carries in the second stage are created using duplicated carry generate (cgd1-cgdi) as well as the carry generates used internally in the adder (cg1-cgi). In Fig.