On-Chip Variable Strobe Time Generator
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
The technique aimed at simplifying the external timing requirements for the functional operation of high performance memory arrays is known, and contained therein basically is a Timing Generator (TG) design to be implemented on-chip to supply all array timings. This article, by contrast, concerns the further enhancement of that TG design such that it will now supply a variable data output strobe by which means it becomes possible to measure the access time of very high performance embedded arrays to a resolution of one technology block delay. The output variable strobe could therefore be varied with that resolution. Figs. 1, 2A and 2B show the time generator design described in this article. Three timings, Address-In (ADDR-IN) clock, Read/Write (R/W) clock and Data Out (D-OUT) clock, are derived from this generator design.