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Method to Electrically Measure the Lateral Bias of Recessed Oxide Isolation

IP.com Disclosure Number: IPCOM000059898D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
De La Moneda, FH [+details]

Abstract

In this article, a method is described to measure the lateral bias of the recessed oxide (ROX) commonly used to isolate device islands containing MOSFET or bipolar transistors. Wafer-level device dimensions can then be determined by applying this bias to layout dimensions. To precisely define lateral ROX bias, the conventional fabrication steps that yield a ROX structure are reviewed with the aid of Fig. 1. Starting with a p-type substrate 1, a layout-level dimension Wo is transferred onto a stack of oxide-nitride layers 2-3 by means of masking and etching operations. This leaves an oxide-nitride mask which defines the device region 4. Its dimensions are smaller than those of the layout since the photoresist is positive and the etching of layers 2-3 is isotropic.