Static Memory Cell With Inverted Flip-Flop and Diode Couplings
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
The density of low cost, medium performance memory cells utilizing poly-silicon based technology may be significantly improved by burying the bit lines and drain line to minimize metal wiring and by employing P-N diodes for bit rail coupling. In Fig. 1, which illustrates a memory cell featuring inverted flip-flop transistors and diode couplings, the drain line (DL) 2 and bit lines (BL) 3 and 4, are buried, and Read/Write diodes 5 and 6 integrated with the polysilicon base 7. Adjacent cells and diodes on the same DL and BL's are separated by 'reach through'. Only four contacts per cell (8, 9, 10, and 11) are necessary (in the absence of metal stitchings) with the merged-transistor logic (MTL) configuration shown, as compared to the ten contacts required of a complementary-transistor-switch (CTS) cell configuration.