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Memory Cells With NPN Couplings

IP.com Disclosure Number: IPCOM000059935D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

Various configurations of bipolar 6-device memory cells exist which emphasize small area and speed or ease of Read and Write operation. In order to reduce the cell area on the chip, Read/Write couplings are generally accomplished in these designs by the employment of SBD's (Schottky barrier diodes), emitters or PNP devices. The 6-device medium performance memory cell described in this article uses no SBD's but achieves its small size by use of inverted NPN couplings. Fig. 1 illustrates the layout of memory cells with NPN couplings. Layout size is kept small by use of merged PNP and NPN devices (1, 2, 5 and 6), as well as integrated NPN's (3 and 4). Bases of NPN devices are connected through the poly-silicon 7. Collectors of 3 and 4 are connected to Bit Lines (BL) 8 and 9.