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Digital Control of Substrate Voltage

IP.com Disclosure Number: IPCOM000059962D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Erdelyi, CK Hoffman, WK [+details]

Abstract

By using feedback of actual chip performance to control chip substrate voltage, power dissipation is held to the lowest level required to maintain adequate performance. This feedback control technique permits tighter control of power-performance specifications, even though there is a wide statistical spread in chip characteristics affecting power and performance. This technique utilizes the substrate voltage sensitivity of field-effect transistor (FET) devices and circuits to optimize the power consumption and the performance of FET integrated circuits. In a given circuit technology, a fixed circuit displays a constant power- delay product. This means that reducing delay also means increasing power, and vice versa.