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Underlayer for Polycide Process

IP.com Disclosure Number: IPCOM000059965D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Ahn, KY Basavaiah, S Iyer, S Joshi, RV [+details]

Abstract

Described below is a process used in forming the gate of a self-aligned MOSFET. More specifically, the process disclosed prevents delamination of a refractory metal silicide layer on a polysilicon layer of the gate terminal by providing an intermediary layer of titanium. Refractory metal silicides (such as tungsten silicate) are used on polysilicon gates in VLSI applications to increase conductivity and are necessary in many applications. However, interfacial stress at the polysilicon-metal silicate interface often results in delamination. One solution to the above problem is to provide excess silicon to the silicide layer to yield a non-stoichiometric composition to increase adhesion. This solution, however, exhibited lower conductivity and greater variation in etching characteristics.