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Decoder Circuit for Processing Logically Redundant Differential Pair Inputs to Static CMOS Circuits Disclosure Number: IPCOM000059975D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

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Hickson, JB Wilcke, WW [+details]


This publication describes a circuit that provides valid outputs for use by static CMOS circuits, from logically redundant DCVS inputs which may be partially erroneous. VLSI (very large-scale integration) may incorporate redundant circuitry to improve yield, reliability, costs, and other factors. One part of a VLSI chip may include redundant units "A" and "B", which generate signals to be used in unit "C". The units "A" and "B" may generate both true and complement signals, which is always the case for DCVS (differential cascode voltage switch) circuits and is sometimes the case for other implementations too. Unit "C", as shown in Fig. 1, may incorporate the static CMOS decoder circuit described here to analyze the redundant differential inputs from units "A" and "B".