High Performance CMOS Logic Gate
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08
In this publication an improved CMOS logic gate structure is described which is an alternative solution to the slow rise delay of large CMOS logic structures caused by the low hole mobility and the large p- channel device body effect, and which does not require an increase in chip (or gate) area. The improved logic gate replaces the complicated pullup structure with a p-channel device whose gate is grounded. Essentially this is the CMOS implementation of an nMOS gate with a depletion-type pullup. This will result in a faster rise delay since it resolves the problem of large p-channel device body effect. Unfortunately, the grounded gate alone is not sufficient to reduce the delay to the order of 6.5 nanoseconds that would be achieved with broken up gates.