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High Performance CMOS Word Decoder Disclosure Number: IPCOM000059982D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

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Braceras, GM Gabric, JA Roberts, AL Tong, MH [+details]


A complementary metal oxide silicon (CMOS) word decoder circuit is described which features simplicity, high performance, and insensitivity to floating nodes. Referring to the circuit diagram, (Fig. 1), simplicity is achieved by the use of transistor T7, which precharges node B high when the true/complement zero (T/C0) is reset at the end of a cycle. By obviating the need for a separate reset line, circuit operation is realized with only one precharge clock CLKP. Transistor T7 actively clamps the word line WL low during the unselected case in which node A floats. Transistor T3 is used to clamp node A high during the selected case, i.e., when inputs T/C 1-n are all low T/C0 is high. High performance is achieved by not requiring clocking after the address lines have switched.