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Inferred On-Chip Waveform Delay Measurement Technique

IP.com Disclosure Number: IPCOM000060002D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Hopkins, DH [+details]

Abstract

The Inferred On-Chip Waveform Delay Measurement Technique is a method for determining experimentally the separate intrinsic turn-on and turn- off logic circuit block delays. This technique is an improvement over the Delay Difference Technique disclosed in [*]. Basically, the intrinsic logic circuit block delay is measured by subtracting two out-of-phase chain delays as shown in the figure, where blocks 1-3 represent internal circuits and block 4 represents an off- chip driver. The turn-on delay of block 1 equals: (rise-to-rise delay A-C) - (fall-to-rise delay B-C) This subtractive technique is correct if the waveforms at "A" input to logic block 1 and the out-of-phase signal at the "B" input to logic block 2 are representative of reality (i.e., have correct signal characteristics).