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Pipelined Carry-Lookahead Adder for Fixed-Point Arithmetic

IP.com Disclosure Number: IPCOM000060026D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Sinha, B [+details]

Abstract

A technique is described whereby pipelined architecture for a carry- look-ahead (CLA) adder achieves high throughput rates for fixed-point add operations. A method to pipeline a sixteen-bit fixed-point CLA adder is described. By following the same procedure, this method can be extended to thirty-two, sixty-four or higher number of strings. A standard sixteen-bit fixed point CLA adder using carry-propagate/generate units and a carry-look-ahead unit is shown in Fig. 1. The eight inputs to the look-ahead unit are generated from block carry propagate/generate units. Four-bit blocks 11 generate the block outputs P1j 12 and G1j 13 for j=0, 1, 2 and 3. The carry outputs 14 are connected to the block carry inputs in the first level, which finally calculates the sum.