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Semi-Self-Aligned Contact for Semiconductor Circuits

IP.com Disclosure Number: IPCOM000060029D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Bausmith, RC Geffken, RM Nesbit, LA [+details]

Abstract

A method is shown for forming a semi-self-aligned contact between upper levels of wiring and the gate electrode of a field-effect transistor (FET), resulting in improved densities. Dense CMOS random-access memories and logic circuits require many contacts between the FET gate electrodes and upper levels of wiring. These contacts consume a large amount of the available chip area, so that device density consistent with minimum lithographic dimensions cannot be fully realized. Fig. 1 shows the cross-section of a gate region of an FET. A gate electrode 10 is patterned atop an oxide layer 8 formed on the silicon wafer 11. The exposed surfaces of gate electrode 10 are oxidized to form oxide layer 12.