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Gate Oxide Protection by Early Polysilicon Deposition

IP.com Disclosure Number: IPCOM000060103D
Original Publication Date: 1986-Feb-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Schnur, SG Spencer, OS [+details]

Abstract

The gate dielectric surface of a CFET or NMOS device can be severely degraded by subsequent process steps, including ion implantations and photoresist strips. Each of these steps possesses the potential for degrading the gate dielectric characteristics. The deposition of a conformal layer of polysili approximately 30 nanometers on the gate oxide, prior to any subsequent process steps will protect it from degradation.