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Dual Processing for Signal Processors

IP.com Disclosure Number: IPCOM000060132D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Beraud, JP [+details]

Abstract

In general, in signal processors data memory and instruction memory have separate busses to allow simultaneous accesses to be made. The minimum cycle time is dependent on the access time and on internal cycle time. To increase the processing power, the processors are duplicated and means are provided to facilitate the exchange between the two processors sharing the same data memory. The contention problem is solved by multiplexing the random-access memory (RAM). Processor 1 has a complete cycle to perform internal processing; the second half of the cycle is used for accessing to the RAM. Processor 2 cycle is delayed by one half of a cycle to allow the RAM to be accessed when processor 1 is disconnected.