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Process for Etching Multilayer Polycide Films

IP.com Disclosure Number: IPCOM000060147D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Bergendahl, A Duncan, B Hakey, M Horak, D [+details]

Abstract

This article describes a two-step etch process (with a clean step in between) to achieve a highly directional and selective etch of an unannealed multilayer polycide film structure in a field-effect transistor fabrication process. The etch requirements are: 1) A near vertical sidewall of the etched silicide to allow for a lightly doped drain (LDD) structure. 2) No shorting of silicide lines. Fig. 1 shows a cross-section of an unannealed multilayered polycide film stack to be etched. It should be noted that the vertical film thickness at B and C is not equal. Because etch end point is critical, the difference in vertical film thickness is one of the problems this etch technique overcomes. A parallel plate center pump reactive ion etch (RIE) tool is utilized for both etch steps.