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Structure to Prevent Latch-Up of CMOS Devices

IP.com Disclosure Number: IPCOM000060160D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Matino, H Wang, LK [+details]

Abstract

This article relates generally to integrated circuit fabrication and, more particularly, to an implantation technique for preventing latch-up conducting of CMOS devices. Latch-up currents and base-collector leakage currents in parasitic pnp and npn transistors in pnpn CMOS devices can be suppressed by selective ion implantation to obtain a short lifetime conduction region under the isolation oxide. In the figure, a complementary CMOS pnpn device using an n-well in a p-type substrate 1 has recessed oxide regions 2 serving as isolation barriers. The usual latch-up current paths are indicated by dashed lines 3. Latch-up currents are suppressed, however, by using ion implantation in selected regions 4 to establish short lifetime conduction.