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Overlay Characterization Technique for Exposing Integrated Circuit Wafers

IP.com Disclosure Number: IPCOM000060169D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Chappelow, RE [+details]

Abstract

This article describes a method by which integrated circuit overlay errors may be substantially reduced through the utilization of a characterization technique designed to correct field-to-field overlay errors on each wafer. All significant causes of wafer exposure alignment errors on photolithographic tools including magnification, alignment offsets, table skew, sample rotation, trapezoidal errors, etc., may be corrected in real time using this new technique. Procedure: 1) Perform global alignment on the wafer in the usual manner. 2) Using a die-to-die alignment system, expose selected chip sites. In addition to the tool's normal function of alignment and exposure, gather position data as if the tool were also a measurement system. Typically, 2-6 chip sites are selected for sample data.