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Static RAM Cell Structure

IP.com Disclosure Number: IPCOM000060178D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Chin, D Matino, H [+details]

Abstract

This article relates generally to solid-state memory cells and, more particularly, to fabrication of static random-access memory (RAM) cell requiring no more surface area than a dynamic RAM cell with a planar or trench capacitor. Static RAM cells employing a tunnel diode and depletion FET, such as those shown in the p-well and n-well versions of Figs. 1a and 1b, respectively, require less substrate area by forming the depletion device within an open-bottom trench and butting the voltage source contact on the recessed oxide region. Depletion implant is done after trench formation. An example of a fabrication process for the static RAM cell of the n-well version is given below: In Fig. 2, a graded n-well 1 is formed in substrate 2, and oxide, nitride and oxide layers 3,4,5, respectively, are deposited.