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Substrate Bias Generator Utilizing Hole Extraction for Latch-Up Prevention of CMOS Circuitry

IP.com Disclosure Number: IPCOM000060253D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Dovek, MM Hanafi, HI [+details]

Abstract

This article describes a structure designed to eliminate CMOS circuit susceptibility to latch-up due to substrate bias generators. The structure includes a substrate bias generator which utilizes hole extraction to bias the p-type substrate to a negative potential in an n-well CMOS technology and hence will avoid circuitry latch-up. Substrate generators designed completely in n-channel FET devices can cause latch-up if utilized with CMOS circuitry. This is because, in the n-channel design, some of the n-diffusions in the generator can be temporarily at a potential lower (more negative) than that of the substrate. This will forward bias these junctions, resulting in electron injection into the substrate and eventually latch-up of the neighboring CMOS circuitry.