Browse Prior Art Database

Wire Matrix

IP.com Disclosure Number: IPCOM000060292D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Long, GB Patel, PT Seewann, E Villarubia, PG [+details]

Abstract

A wiring arrangement that can be used in the design of CMOS chips is described. In the design of chips there are typically large areas containing only wiring, no circuits. The wiring in these areas can be replaced by a Wire Matrix (WM). The reduction in size is accomplished by using both first- and second-level metal along one axis while using diffusion along the other axis. This wiring has a large increase in density over second metal and a smaller increase over first metal. The major incentive for using the WM is wiring pitch. Traditional wiring consists of busses composed of either first or second metal lines in a given wiring dimension. For many chips, second metal has been used for most of the horizontal data flow, while first metal is used for the vertical data flow.