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Partial Polycrystalline Silicon-Filled Trench for VLSI Disclosure Number: IPCOM000060322D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

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Kemlage, BM Tsang, YL [+details]


Over-planarization may occur in polycrystalline silicon-filled trench (PST) isolation processes for VLSI (very large-scale integration) in semiconductor devices. This recesses the fill below the wafer surface and may expose epitaxy regions causing electrical shorts. In addition to N-epi shorting to the substrate, stress can result from oxidizing the filled poly-Si through poly-Si voids in the deep trench region. This article proposes a process for protecting the poly at appropriate steps so as to overcome these problems. Fig. 1 shows the various films on N-type epi 8 grown on p-type silicon substrate 3 by means of a standard PST (poly-silicon trench) process.