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Voidless Final Closure Process for Polysilicon Trench

IP.com Disclosure Number: IPCOM000060343D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Ghez, RA Silvestri, VJ [+details]

Abstract

In the manufacture of semiconductor devices, voids can form in the polysilicon trench (PST) refill process. This article proposes a high rate poly-Si deposition followed by a low rate poly-Si deposition which acts to reduce the incidence of voids. For vertical wall trenches the conformal stage growth rate is depicted in Fig. 1. The growth rate from the pre-nucleated LPCVD (Low Pressure Chemical Vapor Deposition) poly film 4 is uniform on all surfaces and is essentially equal to the rate of growth on a blanket silicon surface for the high temperature poly-Si refill 1. Insulators 3 delineate the sidewalls in the Si 2. A SiCl4-H2 reaction at 1000ŒC is used for the bulk of the fill. At a later stage in the process, due to some enhancement of growth from the bottom corners, a cusp 5, Fig. 2, forms within the trench.