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Low Temperature Anneal to Enhance Yield and Reliability Improvement by Eliminating Parametric Degradation

IP.com Disclosure Number: IPCOM000060378D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Chaudhari, PK [+details]

Abstract

In the manufacture of field-effect transistors (FETs) there exists a problem of threshold voltage shift of the devices under temperature and bias stress. This problem is alleviated by annealing these devices at low temperatures so as to eliminate the impact of hot electron trapping at moisture-related traps on the Vt shift. In LSI/VLSI IC (large-scale integration/very large-scale integration integrated circuit) technology, parametric degradation has been a reliability concern. This is especially so with a hot electron trapping-induced threshold voltage shift which may result in malfunction of the device. The problem becomes more severe as the physical dimensions of these devices shrink.