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Method for Removing Redundancies From Programmable Logic Arrays Disclosure Number: IPCOM000060391D
Original Publication Date: 1986-Mar-01
Included in the Prior Art Database: 2005-Mar-08

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Popp, DE [+details]


A programming concept makes is possible to reduce logic redundancies in a PLA (Programmable Logic Array) without converting the product terms to their Boolean equivalents. This permits the designer to work with a familiar format and reduces processing time, at the expense of a less than completely optimum reduction. A value is determined for each product term to establish a sort list in descending value order. Each product term is then compared successively with all other product terms, testing for one of four conditional rules. Depending on conditions detected in each comparison, product terms or elements of them may be deleted. Successive passes through the list are made until no further deletions are detected. A PLA consists of an input (AND) array and an output (OR) array. Fig.