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Master Image Layout With Macro Capability

IP.com Disclosure Number: IPCOM000060404D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Cox, DT Donze, RL Merkel, DA Sanders, JJ Satre, PS [+details]

Abstract

Master image chips were designed to handle a variety of different random logic books. As density of the chips grows, the requirement for macros increases. The figure shows the layout of a master image chip. The major requirements of this macro approach are to retain excellent wirability, to fit into the power busing scheme, and to ensure physical to logical integrity. Power bus integrity is retained by placing several limitations on macro physical designs. The macros have custom power buses and do not pass them through. This means the macros have to be placed at the ends of the first metal power buses, which come off one central second level power bus down the center of the chip. This placement ensures that no logic book can be disconnected from power by the placement of a macro between it and the second metal power bus.