Browse Prior Art Database

Gate Level Self-Test for Field-Replaceable Unit

IP.com Disclosure Number: IPCOM000060426D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Diehl, CM Lewis, HW [+details]

Abstract

Each gate in a system design has a socket that is wired to accommodate a self-test field-replaceable unit (STF). The STF contains a linear feedback shift register (LFSR) that generates pseudo-random patterns, a multi-input shift register (MISR) for signature compression, compare circuitry, a read-only memory (ROM) containing the final signatures of each field-replaceable unit (FRU) in the gate, and clock/control circuitry for self-test. When the STF 1 is plugged into the gate, and activated, each partition in the gate is fed the appropriate clock signals via the STF clock/control 2 and pseudo-random patterns from the LFSR 3. The output of each level sensitive scan design (LSSD) scan string in the partition will be fed back into the MISR 4.