Dual-Ported Bus Structure With Asynchronous DMA Handshake
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
This article describes a bus structure that provides high direct memory access (DMA) data rates, low overhead for the communicating units' processors and a flexible method of command/data transfer between the intelligent units without bus arbitration with its accompanying performance overhead and complexity. The structure is seen in Fig. 1. Units A, B, and C are all functional units containing microprocessor systems. A's do not communicate with other A's, but all A's communicate with B and B with all A's. B and C also communicate with each other. D has no microprocessor and is tightly bound to C with a special bus. The A to B interface is seen in Fig. 2. The "A" units contain both a Command Port and a DMA Port. They are memory mapped into both the address space of the A unit and the address space of the B unit.