Memory Data Hold Register
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
The figure illustrates the use of a memory interface which permits the coupling of a slow core memory circuit or a fast integrated memory circuit to a plurality of processors. A processor 10 includes, at least, an instruction register 12, a data register 14, a microcode register 16 and a program counter 18. In executing an instruction, the processor 10 generates and transmits a bus request to a memory system 20. Outputs of the program counter 18 are coupled to a memory address expansion RAM (random-access memory) 22 and a memory address register 24. The program counter 18 and the memory address expansion RAM 22 facilitate the generation of an expanded address which is stored in the memory address register 24. The expanded address enables the addressing of a larger number of memory cells in the memory system 20.