Browse Prior Art Database

Lagging Address Register Mechanism

IP.com Disclosure Number: IPCOM000060465D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Laurent, B Poiraud, C Sazbon-Natansohn, D [+details]

Abstract

The Lagging Address Register (LAR) is a "came from" register. When displayed by the operator or by the program, the LAR contains the address of the last instruction executed prior to the instruction that is currently being executed, if any. The LAR mechanism is intended to help the programmer in knowing the address of the last instruction executed prior to the occurrence of specific events, such as programming errors, data protection errors, adapter communication errors, etc. The control program can load the contents of LAR into a general register by executing an input instruction. The control program can then either examine the contents of the general register or display the address on the control panel by using the general register as input to the display registers. The LAR register updating mechanism is shown in Fig. 1.