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Trigger Circuit With Hysteresis

IP.com Disclosure Number: IPCOM000060471D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Scheuerlein, RE [+details]

Abstract

A trigger circuit is described which improves the performance of high density complementary metal-oxide-silicon (CMOS) dynamic random-access memories (DRAMs). During a memory cell access, the trigger circuit senses the word line transition and provides a delay to permit full signal transfer before initiating the bit line sensing operation. The circuit incorporates a high degree of hysteresis in its transfer characteristic, having a high unity gain point for rising inputs and a low unity gain point for falling inputs. The trigger circuit, as shown in Fig. 1, is implemented using a CMOS NAND gate along with a CMOS inverter and transistors TP1, TP2, TN1, and TN2.