Browse Prior Art Database

Separate Microcode-Controlled WRITE Lines for DATA and ECC CHECK Bits

IP.com Disclosure Number: IPCOM000060487D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Burmeister, WF Hughes, JE King, J Preston, DC Saxenmeyer, G [+details]

Abstract

By the use of separate microcode-controlled write lines for data and error correction code (ECC) check bits, errors can be forced into the data or check bit portions of a main storage array in order to completely test ECC logic or isolate failing memory chips. Any number of bits can be easily altered to improve diagnostic capabilities. As an example, single, double, or triple bit errors can be forced via microcode. A minimal amount of hardware, two latches, and one buffer/driver accomplish the error force. Referring to the figure, assume an error is to be forced into the data at location "A"of the Data Array. Good data is used to generate the check bits in the ECC logic. The CHECK BIT WRITE ENABLE latch 1 is set, and the check bits are written into location "A" of the Check Array.