Browse Prior Art Database

S370 Timer Hardware for PC/370 System

IP.com Disclosure Number: IPCOM000060503D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Boguski, MJ Houghtalen, SR Hughes, JE Schappe, TL [+details]

Abstract

The current implementation of S/370 Timers in the PC/370 uses the PC timer facility. This provides a resolution of approximately 55 milliseconds for the time of day counter (TODC), central processing unit (CPU) Timer and Clock Comparator. This resolution is too low for many S/370 applications. Higher resolution is provided by implementing the timers with a combination of hardware and microcode. The hardware is a small amount of otherwise unused circuitry available in a new implementation of PC/370. This implementation provides TODC resolution of 16 microseconds and CPU Timer and Clock Comparator resolution of 256 microseconds. The hardware contains a 12-bit counter 1 which has a resolution of 16 microseconds and a period of 64 milliseconds. When the counter overflows, the hardware generates an interrupt to the microcode.