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Method to Achieve CMOS ROX Isolation Using Lift-Off for Self-Aligning Implanted Areas

IP.com Disclosure Number: IPCOM000060514D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Dally, AJ Ogura, S Rovedo, N [+details]

Abstract

In the manufacture of semiconductors, there are various approaches to achieving ROX (recessed oxide) isolation in the CMOS (complementary metal oxide semiconductor). An invention proposes a method to achieve isolation which would eliminate one of the three masks required in the process. When using ROX for CMOS there is the need to offset the N well from the ROX edge. This is to avoid shorting the N well to the p-epi, and to avoid "sidewalk" beneath the poly-Si gate. The problem is illustrated in Fig. 1. The basic structure is shown in Fig. 1A, Si3N4 layer at 1, SiO2 at 2 and field implant doping at 3. In Fig. 1B, the N well implant 4 is not particularly high (about 1012 atoms/cc) and cannot compensate for the encroachment of P+ .