Hardware Implementation of a Fast Transitional Recorder for Logic and Timing Analysis
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
A transitional recorder logic circuit is disclosed which replaces traditional random memory addressing and decoding with a sequential shift register memory having both timing and sense information. The timing and sense information in the register is comparatively updated at high speeds during a test sequence. The logic circuit eliminates the need for address registers and address decode logic while maximizing the use of available memory by having a common storage for trigger words and sense information. The figure shows a schematic block diagram of the transitional recorder logic circuit 10. The circuit is comprised of a shift memory register 11 having inputs from a latch logic module 12, clock counter 13 and AND gate 15 and output to a comparator 14.