Hardware Interrupt Vectoring Circuit for Non-Compatible Peripherals
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08
A technique is described whereby a circuit provides software programmable hardware vectoring of peripheral interrupts. The circuit is particularly useful to interface with processors which utilize multiple interrupt acknowledge cycles in the performance of interrupt vectoring. The circuit allows direct vectoring into interrupt service routines for peripherals which are not normally directly compatible with a processor's interrupt acknowledge circuitry. There are many peripheral devices which have the capability of placing a vector address or a portion of an address on their data bus, such as a communication controller. However, there are various families of peripherals which use different interrupt acknowledge sequences that prevent direct connection to a processor.