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Scr-Free CMOS Structure

IP.com Disclosure Number: IPCOM000060521D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Bhatia, HS Bhatia, SS Bogart, SG [+details]

Abstract

CMOS technology is very attractive because low power circuits can be designed with it. However, the currents generated in the parasitic bipolars can result in latch-up of the entire circuit (Fig. 1). In this configuration the collector current of the PNP is base current for the bipolar NPN, and vice versa. This phenomenon results in latch-up of the circuit. This article describes a circuit structure (Figs. 2A and 2B) that provides two additional diffusions 10 and 20 of the same conductivity as the source/drain of adjacent FETs and are connected to separate drain lines. In this configuration, the parasitic currents of the NPN bipolar are divided into drainage line current IC2 and regular current IC1 .