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Basic Internal Circuit Cell Using Submicron Devices Disclosure Number: IPCOM000060563D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

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Lo, TC Montegari, FA Swietek, DJ [+details]


A particular cell layout is described which utilizes submicron field- effect transistor gates. The wiring process uses platinum areas in addition to the normal first-level wiring metal. The use of the platinum areas increases the number of first-level wiring channels. An example of one of the circuits which can be made from the cell is shown. Fig. 1 shows the basic cell layout at a stage when the wafer is partially processed. This cell forms part of an overall semiconductor chip pattern of a gate-array type. Areas 1, 2, 3 and 4 are N-pockets with the polycrystalline silicon (poly) lines 5, 6 and 7 forming the gate connections to create four N-type, MOS-type transistors 8, 9, 10 and 11 . Area 18 is a deep diffused N-well, with N-pockets 19 and 20 contained therein.