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Programmable Resistors

IP.com Disclosure Number: IPCOM000060565D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Favata, AF Gaudenzi, GJ Ippolito, PM Kroesen, R Siegel, JD [+details]

Abstract

An embedded resistor technique is disclosed in this article which offers a high level of reliability and programmability while keeping device area consumption to a minimum. General aspects of the disclosed resistor design technique are shown in the figures, and four interesting features unique to it are described below. 1) The resistor bed, as shown in the figures, is surrounded by ROI (recessed oxide isolation). This isolates it from neighboring resistor beds, thereby completely eliminating the danger of parasitic p-FET formation, enhancing reliability, and allowing unrestricted wirability across adjacent resistor beds. 2) The positive contact of the resistor is so designed as to maximize its area of contact, thereby compensating for contact depletion failure mechanisms at this contact.