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Receiver Circuits With High Noise Tolerance Disclosure Number: IPCOM000060569D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

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Kikuchi, D Reedy, DC [+details]


A receiver circuit is disclosed that offers an improved device count as compared to current switch circuit approaches, and attains a high noise tolerance. The receiver circuit shown in the drawing operates from 10-100"C at a supply voltage of 3.0 volts +/- 10% and has 380 mvolts of dc noise tolerance (assuming a worst-case ground rise of 50 mvolts). This high noise tolerance is attained through hysteresis provided by the Schottky barrier diode S1. The input threshold depends on the previous state of the circuit. The rising threshold level is equal to the transistor T3 base- emitter voltage plus the transistor T2 base-emitter voltage minus the transistor T1 collector-emitter voltage. The S1 diode is not conducting.