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High Performance 32-Bit Shifter in CMOS Technology Disclosure Number: IPCOM000060591D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

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Leininger, JC [+details]


A technique is described whereby a particular CMOS gate array circuit library is used to perform single 16-bit or 32-bit double left circular, right arithmetic and left logical shifts of various amounts. Also, the concept provides the ability to complement the input data value with only four levels of circuit delay to realize all functions. Many CMOS technology circuit families do not provide wired OR capability. The largest CMOS AND/OR circuit family provides for a maximum of four groups of inputs with a maximum of two inputs in each group. This allows, at most, a four-way multiplexer to be utilized in one stage of delay on a single output signal line.