Method for Equalizing Chip Power Flow
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-09
The number of temperature excursions experienced by a CMOS chip is greatly reduced by incorporating on-chip resistive dummy loads which are used when the chip is in an inactive state. By this means, extended life of reliable chip-to-next wiring level interconnection metallurgy is realized.