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Merged Transistor Push-Pull Read/Write Port Circuit for Multi-Port Array Cells

IP.com Disclosure Number: IPCOM000060672D
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-08

Publishing Venue

IBM

Related People

Authors:
Gittleman, D [+details]

Abstract

A single read/write port circuit replaces one read port circuit and one write port circuit by use of the described 'merged transistor push-pull read/write port circuit' (MTPPRWPC) with a resultant savings of silicon and metal areas for chip application, i.e., denser chips, by the elimination of two bit lines, one word line, one resistor and two transistors per read/write port. Each multi-port array cell is connected through its MTPPRWPC to two bit lines and one word line per read/write port, as shown in Fig. 1. The MTPPRWPC operates as follows: The sense bit line 3 has two states: 'down' (presenting a high impedance to the NPN-collector-PNP-base node) and 'up'. The data in bit line 4 also has two states, 'down' and 'up', and the word line 5 has three states, 'down', 'intermediate' and 'up'.