Reduction of Trace Requirements for Logic Simulation
Original Publication Date: 1986-Apr-01
Included in the Prior Art Database: 2005-Mar-09
Saving the values of every internal net in each chip under test in a simulation run requires large central processing unit and direct access storage device overhead. Instead of saving the value of every internal net, record only those changes that occur in storage elements and primary inputs. The program used to display the simulation results is used to generate the value of the other internal nets by executing the logic model of the chip (or logic group) containing it. By using the values of the inputs and storage elements the resulting display of internal nets is the equivalent to the prior method.