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Process for Making a Two-Device Non-Destructive Read-Out Memory Cell in a Three-Dimensional Structure Disclosure Number: IPCOM000060704D
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09

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Landler, PF [+details]


A process is described which utilizes trench structure and processing to build a non-destructive read-out (NDRO) memory cell comprised of one p-type transistor, one n-type transistor and a capacitor. The process results in utilization of three dimensions for transistor construction, minimizing the amount of surface area required for the cell. The circuit shown in Fig. 1 is the final product of the process to be described. The bit line B/L is connected to the source of transistor T2 (p-type) and to the source of transistor T1 (n-type). The gate of transistor T2 is connected to the write enable line W/E. The drain of transistor T2 is connected to the gate of transistor T1 and to the upper plate of capacitor C. The word line W/L is connected to the lower plate of capacitor C and to the drain of transistor T1.