Stackable "J" Leaded Chip Carrier
Original Publication Date: 1986-May-01
Included in the Prior Art Database: 2005-Mar-09
This design provides molded-in features that permit "J" leaded chip carriers to be stacked. This increases packaging density and is especially useful in memory applications. The design differs from that presented in [*] in that in this design top and bottom packages are identical. There are no special lead form requirements and no unique bosses on either package. Either package can be used by itself or in a stacked configuration. In the showing of the figure, corresponding parts of the lower and upper packages are given the same reference number, except that the upper package members are primed. As shown, die 10, around which each lead 12 is formed, is chamfered (as seen at 14) and the dies 10' of the upper package 16 rest in a corresponding chamfered notch 18 provided in the top of the lower carrier 20.